document number: 91260 www.vishay.com s11-0111-rev. c, 07-feb-11 1 power mosfet irfps40n50l, SIHFPS40N50L vishay siliconix features ? superfast body diode eliminates the need for external diodes in zvs applications ? lower gate charge results in simpler drive requirements ? enhanced dv/dt capabilitie s offer improved ruggedness ? higher gate voltage threshold offers improved noise immunity ? compliant to rohs directive 2002/95/ec applications ? zero voltage switching smps ? telecom and server power supplies ? uninterruptible power supplies ? motor control applications notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. starting t j = 25 c, l = 0.86 mh, r g = 25 ? , i as = 46 a (see fig. 12). c. i sd ? 46 a, di/dt ? 550 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. product summary v ds (v) 500 r ds(on) ( ? )v gs = 10 v 0.087 q g (max.) (nc) 380 q gs (nc) 80 q gd (nc) 190 configuration single n-channel mosfet g d s g d s super-247 available rohs* compliant ordering information package super-247 lead (pb)-free irfps40n50lpbf SIHFPS40N50L-e3 snpb irfps40n50l SIHFPS40N50L absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 continuous drain current v gs at 10 v t c = 25 c i d 46 a t c = 100 c 29 pulsed drain current a i dm 180 linear derating factor 4.3 w/c single pulse avalanche energy b e as 920 mj repetitive avalanche current a i ar 46 a repetitive avalanche energy a e ar 54 mj maximum power dissipation t c = 25 c p d 540 w peak diode recovery dv/dt c dv/dt 34 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91260 2 s11-0111-rev. c, 07-feb-11 irfps40n50l, SIHFPS40N50L vishay siliconix note a. r th is measured at t j approximately 90 c. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width ? 400 s; duty cycle ? 2 %. c. c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 % to 80 % v ds . c oss eff. (er) is a fixed capacitance that stores the same energy as c oss while v ds is rising from 0 % to 80 % v ds . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient a r thja -40 c/w case-to-sink, flat, greased surface r thcs 0.24 - maximum junction-to-case (drain) a r thjc -0.23 specifications (t j = 25 c, unless otherwise noted) parameter symbol test cond itions min. typ. max. unit static drain-source br eakdown voltage v ds v gs = 0 v, i d = 250 a 500 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 1 ma -0.60- v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 3.0 - 5.0 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v -- 50 a v ds = 400 v, v gs = 0 v, t j = 125 c -- 2.0 ma drain-source on-state resistance r ds(on) v gs = 10 v i d = 28 a b - 0.087 0.100 ? forward transconductance g fs v ds = 50 v, i d = 46 a 21 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 8110 - pf output capacitance c oss - 960 - reverse transfer capacitance c rss - 130 - output capacitance c oss v gs = 0 v v ds = 1.0 v , f = 1.0 mhz - 11200 - v ds = 400 v , f = 1.0 mhz - 240 - effective output capacitance c oss eff. v ds = 0 v to 400 v c - 440 - effective output capacitance (energy related) c oss eff. (er) - 310 - total gate charge q g v gs = 10 v i d = 46 a, v ds = 400 v, see fig. 7 and 15 b -- 380 nc gate-source charge q gs -- 80 gate-drain charge q gd -- 190 internal gate resistance r g f = 1 mhz, open drain - 0.90 - ? turn-on delay time t d(on) v dd = 250 v, i d = 46 a, r g = 0.85 ? , v gs = 10 v, see fig. 14a and 14b b -27- ns rise time t r - 170 - turn-off delay time t d(off) -50- fall time t f -69- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode --46 a pulsed diode forward current a i sm - - 180 body diode voltage v sd t j = 25 c, i s = 46 a, v gs = 0 v b --1.5v body diode reverse recovery time t rr t j = 25 c, i f = 46 a - 170 250 ns t j = 125 c, di/dt = 100 a/s b - 220 330 body diode reverse recovery charge q rr t j = 25 c, i s = 46 a, v gs = 0 v b - 705 1060 nc t j = 125 c, di/dt = 100 a/s b -1.32.0 reverse recovery current i rrm t j = 25 c - 9.0 - a forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) s d g
document number: 91260 www.vishay.com s11-0111-rev. c, 07-feb-11 3 irfps40n50l, SIHFPS40N50L vishay siliconix typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 0.01 0.1 1 10 100 1000 0.1 1 10 100 20s pulse width t = 25 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 0.1 1 10 100 1000 0.1 1 10 100 20s pulse width t = 150 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 0.1 1 10 100 1000 4 5 6 7 8 9 10 11 v = 50v 20s pulse width ds v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 25 c j t = 150 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d 10v 47a
www.vishay.com document number: 91260 4 s11-0111-rev. c, 07-feb-11 irfps40n50l, SIHFPS40N50L vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical output capacitance stored energy vs. v ds fig. 7 - typical gate charge vs. gate-to-source voltage fig. 8 - typical source dr ain diode forward voltage 1 10 100 1000 v ds , drain-to-source voltage (v) 10 100 1000 10000 100000 1000000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 100 200 300 400 500 600 v ds, drain-to-source voltage (v) 0 5 10 15 20 25 30 35 40 e n e r g y ( j ) 0 100 200 300 400 0 5 10 15 20 q , total gate charge (nc) v , gate-to-source voltage (v) g gs i = d 47a v = 100v ds v = 250v ds v = 400v ds 0.1 1 10 100 1000 0.2 0.7 1.2 1.7 2.2 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 150 c j
document number: 91260 www.vishay.com s11-0111-rev. c, 07-feb-11 5 irfps40n50l, SIHFPS40N50L vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case 25 50 75 100 125 150 0 10 20 30 40 50 t , case temperature ( c) i , drain current (a) c d pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 0.001 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)
www.vishay.com document number: 91260 6 s11-0111-rev. c, 07-feb-11 irfps40n50l, SIHFPS40N50L vishay siliconix fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 12d - maximum safe operating area fig. 13a - gate charge test circuit fig. 13b - basic ga te charge waveform a r g i as 0.01 t p d.u.t. l v ds + - v dd driver 15 v 20 v i as v ds t p 1 10 100 1000 10 100 100 operation in this area limited by r ds(on) single pulse t t = 150 c = 25 c j c v , drain-to-source voltage (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms 25 50 75 100 125 150 0 500 1000 1500 2000 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom 21a 30a 46a d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - q gs q gd q g v g charge v gs
document number: 91260 www.vishay.com s11-0111-rev. c, 07-feb-11 7 irfps40n50l, SIHFPS40N50L vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldw ide manufacturing capability. prod ucts may be manufactured at on e of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents su ch as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91260 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
package information www.vishay.com vishay siliconix revision: 27-mar-17 1 document number: 91365 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-274aa (high voltage) notes ? dimensioning and tolerancing per asme y14.5m-1994 ? dimension d and e do not include mold fl ash. mold flash shall not ex ceed 0.127 mm (0.005") per side . these dimens ions are meas ured at the outer extremes of the plastic body ? outline conforms to jedec ? outline to to-274aa (1) dimension measured at tip of lead millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 4.70 5.30 0.185 0.209 d1 15.50 16.10 0.610 0.634 a1 1.50 2.50 0.059 0.098 d2 0.70 1.30 0.028 0.051 a2 2.25 2.65 0.089 0.104 e 15.10 16.10 0.594 0.634 b 1.30 1.60 0.051 0.063 e1 13.30 13.90 0.524 0.547 b2 1.80 2.20 0.071 0.087 e 5.45 bsc 0.215 bsc b4 3.00 3.25 0.118 0.128 l 13.70 14.70 0.539 0.579 c (1) 0.38 0.89 0.015 0.035 l1 1.00 1.60 0.039 0.063 d 19.80 20.80 0.780 0.819 r 2.00 3.00 0.079 0.118 ecn: x17-0056-rev. b, 27-mar-17 dwg: 5975 a1 a c a2 b e e4 d l e l1 b 0.10 (0.25) b a mm e1 d2 d1 r detail ?a? a b2 b4 detail ?a? scale: 2:1 10 5 lead tip
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